Ranging is the process of determining the distance from one location or position to another location or position. For indoor ranging with submeter accuracy, it is often desirable to use wideband signals. This is because wideband signals may avoid multipath interference, which disturbs the time of arrival measurement. A comparison of multipath interference in wideband and narrowband signals is illustrated in FIG. 1.
An example of a typical ranging system may be that described in WO2007/071748. The proposed indoor ranging system combines the advantages of both broadband and narrowband signals to achieve a high ranging accuracy in presence of strong multipath reflections, to realize a good link budget, and to be compliant with the spectral regulations. The fundamental idea is that relatively narrowband radios, such as those used in wireless local area network (WLAN) products, may exhibit and/or can be stimulated to exhibit wideband transient signals at the beginning of the packet.
One possible way to realize a fast enabling of the packet is to use a radio frequency (RF) switch, such as that proposed in “Embedded ranging system in ISM Band” (X. Yin et al., Electronics Letters, Vol. 44, No. 17, pp. 1043-1045, August 2008), or that proposed in “A Novel Positioning Technique for 2.4 GHz ISM Band”, (H. Tubbax, Proc. 4th IEEE Radio and Wireless Symposium, San Diego, USA, January 2009). The wideband transient signals can then be leveraged for improved positioning accuracy at the receiver. In particular, these wideband transient signals can be processed along with the narrowband communication signal. The system uses the same frequency band for both communication and ranging purposes, so that no separate dedicated ranging transceiver is needed. However, in order to achieve low cost and low power consumption, an integrated ranging transceiver is needed.
Power amplifier circuits for ranging applications are often designed employing cascoded transistors. The advantages of a cascode topology have been analysed in detail in the literature (see, for example, “A Common-Gate Switched 0.9-W Class-E Power Amplifier with 41% PAE in 0.25 μm CMOS” (C. Yoo et al., IEEE J. Solid-state Circuits, vol. 36, no. 5, pp. 823-830, May 2001) and “Analysis of Reliability and Power Efficiency in Cascode Class-E PAs” (Mazzanti et al., IEEE J. of Solid-state Circuits, vol. 41, no. 5, pp. 1222-1229, May 2006)). In a non-cascode topology, the maximum drain voltage can be, for example, 3.56 times the supply voltage, and the drain-source breakdown voltage is only 2 to 3 times the typical supply voltage for complementary metal-oxide-semiconductor (CMOS). When a cascode topology is used, on the other hand, the circuit can sustain two times the breakdown voltage of a single transistor, which thus can allow a maximum supply voltage that is almost two times higher. The same output power can be obtained with lower load resistance RL, but the lower RL gives rise to more power loss in the power amplifier, which degrades the efficiency.
Often a CMOS power amplifier is implemented as a class-E power amplifier. The class-E topology makes it possible to reuse the parasitic drain-source capacitance of the switching transistor. A class-E power amplifier circuit is typically used in a switching design for applications where power efficiency is a major issue and where such high frequencies are involved that the switching time becomes comparable to the duty time. Its operation is based on the portion of the input signal cycle during which the amplifying device conducts.
Accordingly, a differential topology is thereby adopted. The differential topology can provide a two times higher output power than the single-ended one. For the same output power, the load resistance of a differential Class-E power amplifier (PA) can be two times higher than that of a single ended one, which thus can have higher efficiency. The topology of the differential cascode Class-E PA is shown in FIG. 2.
Since a ranging Class-E power amplifier requires a very fast switch-on and switch-off speed for performing time-based ranging, a switching function should be added to the circuit. In “A 1.9-GHz, 1-W CMOS Class-E Power Amplifier for Wireless Communications” (Tsai and Gray, IEEE J. Solid-state Circuits, vol. 34, no. 7, pp. 962-970, July 1999), a common-source switch is applied at the common-source node of the input transistors. This is illustrated in FIG. 3. While no speed of the switch is mentioned in Tsai et al., because the common-source switch is on the signal path, which has a finite switch-on resistance, the common-source switch inevitably degrades the drain efficiency of the power amplifier. In order to minimize the effect of the common-source switch, the size of the switch has to be very large, thereby consuming a large area and, in turn, lowering efficiency.
In order to control the output power for the class-E power amplifier, the supply voltage may be tuned. Alternately, when transformers are used to combine the output power of several power amplifiers, the power control can be implemented by switching on and off certain power amplifiers. Other solutions may involve controlling the power by tuning the effective load resistance with varactors with high quality factor or by changing the size of the input transistor. Such techniques, however, typically offer a very limited power control range and low efficiency in low output power levels.
In “Output Power Control in Class-E Power Amplifiers” (Sira et al., IEEE Microwave and Wireless Components Let., vol. 20, no. 4, pp. 232-234, April 2010), the power control is implemented with dynamic cascode bias, since a cascode topology is used. In “A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off,” (M. Apostolidou et al., IEEE J. of Solid-state Circuits, vol. 44, no. 5, May 2009), the power control is implemented with a dynamic supply voltage together with the dynamic self-bias voltage of the self-bias topology. However, with only dynamic drain supply, and with only dynamic cascode bias, the class-E PA cannot provide the optimal drain efficiency in low output power levels.
For the cascode Class-E topology, it has been suggested to control the output power with the dynamic supply voltage. The cascode bias VCG may be direct current (DC) fixed or connected to VDD. However, the optimal cascode bias shifts with the adjusting of VDD. The lower VCG is needed for the optimal drain efficiency when VDD is lower. Hence, dynamic cascode bias is needed to optimize the output power and efficiency for different VDD values. Implementing the power control by adjusting the cascode bias VCG is not a satisfactory solution either, as it also cannot provide the optimal efficiency in low output power levels.